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19-2848; Rev 1; 11/03
KIT ATION EVALU ILABLE AVA
Highly Integrated Level 2 SMBus Battery Charger
General Description Features
Compliant with Level 2 Smart Battery Charger Specifications Rev 1.1 Intel SMBus 2-Wire Serial Interface 0.5% Charge-Voltage Accuracy 11-Bit Charge-Voltage Resolution 3% Input Current-Limit Accuracy Uses Small (10m) Current-Sense Resistors 8A Maximum Charge Current 6-Bit Input and Charge-Current Resolution 8V to 28V Input Voltage Range 175s Charge Safety Timer Automatic Selection of System Power Source Charges any Battery Chemistry (Li+, NiCd, NiMH, Lead Acid, etc.)
MAX1535A
The MAX1535A is a highly integrated, multichemistry battery charger that simplifies construction of advanced smart chargers with a minimum number of external components. It uses Intel's system management bus (SMBus) to control the charge voltage, charge current, and the maximum current drawn from the AC adapter. High efficiency is achieved through use of a constant offtime step-down topology with synchronous rectification. In addition to support of the Smart Battery Charger Specifications Rev 1.1, the MAX1535A includes additional features. The maximum current drawn from the AC adapter is programmable to avoid overloads when supplying the load and the battery charger simultaneously. This enables the user to reduce the cost of the AC adapter. The MAX1535A provides a digital output that indicates the presence of an AC adapter. Based on the presence or absence of the AC adapter, the MAX1535A automatically selects the appropriate source for supplying power to the system by controlling two external P-channel MOSFETs. Under system control, the MAX1535A allows the battery to undergo a relearning or conditioning cycle in which the battery is completely discharged through the system load and then recharged. The MAX1535A is capable of charging 2, 3, or 4 lithiumion (Li+) cells in series, providing charge currents as high as 8A. The DC-to-DC converter in the MAX1535A uses a high-side P-channel switch with an N-channel synchronous rectifier. The charge current and input current-limit sense amplifiers have low input-offset errors and can use small-value sense resistors (0.01, typ). The MAX1535A is available in a 5mm x 5mm 32-pin thin QFN package and operates over the extended -40C to +85C temperature range. An evaluation kit is available to reduce design time.
Ordering Information
PART MAX1535AETJ TEMP RANGE -40C to +85C PIN-PACKAGE 32 Thin QFN (5mm x 5mm)
Pin Configuration
TOP VIEW
ACOK CSSN CSSP DHIV 25 24 DLOV 23 DLO 22 PGND 21 CSIP 20 CSIN 19 BATT 18 GND 17 I.C. 9 VMAX 10 IMAX 11 DAC 12 VDD 13 THM 14 SDA 15 SCL 16 INT PDS SRC 27 PDL DHI 26
32 DCIN 1 LDO 2 ACIN 3 REF 4 GND 5 CCS 6 CCI 7 CCV 8
31
30
29
28
Applications
Notebook and Subnotebook Computers Tablet PCs Portable Equipment with Rechargeable Batteries
MAX1535A
THIN QFN (5mm x 5mm)
________________________________________________________________ Maxim Integrated Products
1
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Highly Integrated Level 2 SMBus Battery Charger MAX1535A
ABSOLUTE MAXIMUM RATINGS
DCIN, CSSP, CSSN, SRC, ACOK to GND .............-0.3V to +30V DHIV to SRC .............................................................-6V to +0.3V DHI, PDL, PDS to GND ...............................-0.3V to VSRC + 0.3V BATT, CSIP, CSIN to GND .....................................-0.3V to +20V CSIP to CSIN, or CSSP to CSSN ...........................-0.3V to +0.3V CCI, CCS, CCV, DAC, REF to GND ............-0.3V to VLDO + 0.3V VDD, ACIN, SCL, SDA, DLOV, LDO, THM, INT, IMAX, VMAX to GND...........................................................-0.3V to +6V DLOV to LDO.........................................................-0.3V to +0.3V DLO to PGND............................................-0.3V to VDLOV + 0.3V PGND to GND .......................................................-0.3V to +0.3V LDO Short-Circuit Current...................................................50mA Continuous Power Dissipation (TA = +70C) 32-Pin Thin QFN (derate 21.3mW/C above +70C) ...1702mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1. VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VDD = 3.3V, ACIN = PGND = GND, LDO = DLOV, VMAX = IMAX = REF, CLDO = 1F, CDHIV = 0.1F, CREF = 1F, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER CHARGE-VOLTAGE REGULATION ChargeVoltage() = 0x41A0 and 0x3130 Charge-Voltage Accuracy ChargeVoltage() = 0x20D0 ChargeVoltage() = 0x1060 ChargeVoltage() = 0x41A0 Full-Charge Voltage ChargeVoltage() = 0x3130 ChargeVoltage() = 0x20D0 ChargeVoltage() = 0x1060 CHARGE-CURRENT REGULATION CSIP-to-CSIN Full-Scale CurrentSense Voltage Compliance Current Accuracy VBATT = 12V 10m sense resistor (R2 in Figure 1) between CSIP and CSIN; ChargeCurrent() = 0x1F80 10m sense resistor (R2 in Figure 1) between CSIP and CSIN; ChargeCurrent() = 0x1F80 Charge Current 10m sense resistor (R2 in Figure 1) between CSIP and CSIN; ChargeCurrent() = 0x0080 BATT/CSIP/CSIN Input Voltage Range CSIP/CSIN Input Current INPUT-CURRENT REGULATION CSSP-to-CSSN Full-Scale Current-Sense Voltage VDCIN = 18V 104.5 110.0 115.5 mV VDCIN = 0V, or charger not switching VCSIP = VCSIN = 12V 0 0.1 300 128 19 1.0 700 mA V A 76.60 -5 7.660 8.064 80.64 84.67 +5 8.467 mV % A -0.5 -0.8 -1.0 16.716 12.529 8.332 4.150 16.800 12.592 8.400 4.192 +0.5 +0.8 +1.0 16.884 12.655 8.468 4.234 V % CONDITIONS MIN TYP MAX UNITS
2
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Highly Integrated Level 2 SMBus Battery Charger
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VDD = 3.3V, ACIN = PGND = GND, LDO = DLOV, VMAX = IMAX = REF, CLDO = 1F, CDHIV = 0.1F, CREF = 1F, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER CONDITIONS 10m sense resistor (R1 in Figure 1) between CSSP and CSSN; InputCurrent() = 0x1580 (11.008A) Input Current-Limit Accuracy 10m sense resistor (R1 in Figure 1) between CSSP and CSSN; InputCurrent() = 0x1000 (8.192A) 10m sense resistor (R1 in Figure 1) between CSSP and CSSN; InputCurrent() = 0x0800 (4.096A) POR (InputCurrent() = 0x0080) CSSP/CSSN Input Voltage Range CSSP/CSSN Input Current VDCIN = 0V VCSSP = VCSSN = VDCIN > 8.0V 8 DCIN falling DCIN rising 8V < VDCIN < 28V VBATT = 19V, VDCIN = 0V, or charger not switching VBATT = 2V to 19V, VDCIN > VBATT + 0.3V 8V < VDCIN < 28V, no load 0 < ILDO < 10mA VDCIN = 8V 3.20 2.7 2.5 100 VDCIN < 6V, VDD = 5.5V, VSCL = VSDA = 5.5V 0 < IREF < 500A REF falling 4.083 17 4.096 3.1 27 4.109 3.9 5.25 7.0 7.4 7.50 2.7 0.1 200 5.40 34 4.00 7.85 6.0 1.0 500 5.50 100 5.15 5.5 2.7 8 0.1 300 MIN -5 -3 -6.5 256 28 1.0 750 28 TYP MAX +5 +3 +6.5 mA V A % UNITS
MAX1535A
SUPPLY AND LINEAR REGULATOR DCIN Input Voltage Range DCIN Undervoltage Lockout Trip Point DCIN Quiescent Current BATT Input Current LDO Output Voltage LDO Load Regulation LDO Undervoltage Lockout Trip Point VDD Range VDD UVLO Rising Threshold VDD UVLO Hysteresis VDD Quiescent Current REFERENCE REF Output Voltage REF Undervoltage Lockout Trip Point TRIP POINTS BATT POWER_FAIL Threshold BATT POWER_FAIL Threshold Hysteresis ACIN Threshold ACIN Threshold Hysteresis ACIN Input Bias Current VACIN = 2.048V ACIN rising VDCIN falling 50 100 1.966 10 -1 100 200 2.048 20 150 300 2.130 30 +1 mV mV V mV A V V V V mA A V mV V V V mV A
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Highly Integrated Level 2 SMBus Battery Charger MAX1535A
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VDD = 3.3V, ACIN = PGND = GND, LDO = DLOV, VMAX = IMAX = REF, CLDO = 1F, CDHIV = 0.1F, CREF = 1F, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER SWITCHING REGULATOR Off-Time DLOV Supply Current Maximum Discontinuous Mode Peak Current Battery Undervoltage Charge Current DHIV Output Voltage DHIV Sink Current DHI On-Resistance Low DHI On-Resistance High DLO On-Resistance High DLO On-Resistance Low ERROR AMPLIFIERS GMV Transconductance GMI Transconductance GMS Transconductance CCI Clamp Voltage CCV Clamp Voltage CCS Clamp Voltage ACOK ACOK Input Voltage Range ACOK Sink Current ACOK Leakage Current PDS, PDL SWITCH CONTROL PDS Switch Turn-Off Threshold PDL Switch Turn-On Threshold PDS Switch Threshold Hysteresis PDL Switch Threshold Hysteresis PDS Output Low Voltage, PDS Below SRC PDS Turn-On Current PDS Turn-Off Current PDL Turn-On Resistance PDL Turn-Off Current PDL and PDS Transition Delay Time DCIN with respect to BATT, DCIN falling DCIN with respect to BATT, DCIN falling DCIN with respect to BATT DCIN with respect to BATT IPDS = 0V PDS = SRC VPDS = VSRC - 2V, VDCIN = 16V PDL = GND VCSSN - VPDL = 1.5V PDS and PDL are unloaded 8 6 10 50 6 4 50 50 100 100 200 200 10 12 50 100 12 10 15 150 12 150 150 mV mV mV mV V mA mA k mA s V ACOK = 0.4V, ACIN = 1.5V V ACOK = 28V, ACIN = 2.5V 0 1 1 28 V mA A ChargeVoltage () = 0x41A0, VBATT = 16.8V ChargeCurrent () = 0x1F80, VCSIP - VCSIN = 80.64mV InputCurrent () = 0x1580, VCSSP - VCSSN = 110.08mV 0.25V < VCCI < 2.0V 0.25V < VCCV < 2.0V 0.25V < VCCS < 2.0V 0.0625 0.5 0.5 150 150 150 0.1250 1 1 300 300 300 0.2500 2 2 600 600 600 A/mV A/mV A/mV mV mV mV VDHI = VDHIV, IDHI = -10mA VDHI = VSRC, IDHI = 10mA VDLOV = 4.5V, IDLO = 100mA VDLOV = 4.5V, IDLO = -100mA VBATT = 2.6V per cell With respect to SRC -4.5 10 4 1 4 1 7 3 7 3 VBATT = 16.0, VDCIN = 21.0 VBATT = 19.0, VDCIN = 21.0 ChargerMode() = 0x0001 540 230 600 270 5 0.5 128 -5.0 -5.5 660 310 10 ns A A mA V mA CONDITIONS MIN TYP MAX UNITS
4
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Highly Integrated Level 2 SMBus Battery Charger
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VDD = 3.3V, ACIN = PGND = GND, LDO = DLOV, VMAX = IMAX = REF, CLDO = 1F, CDHIV = 0.1F, CREF = 1F, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER PDL-to-PDS Switchover Time in Relearn Mode VBATT to VVMAX Ratio VMAX Input Voltage Range VMAX Input Bias Current ICHARGE to VIMAX Ratio IMAX Input Voltage Range IMAX Input Bias Current THERMISTOR COMPARATOR Thermistor Overrange Threshold Thermistor Cold Threshold Thermistor Hot Threshold Thermistor Underrange Threshold Thermistor Comparator Hysteresis SDA/SCL Input Low Voltage SDA/SCL Input High Voltage SDA/SCL Input Bias Current SDA, INT Output Sink Current INT Output Low Voltage SMBus Frequency SMBus Free Time Start Condition Setup Time from SCL Start Condition Hold Time from SCL Stop Condition Setup Time from SCL SDA Hold Time from SCL SDA Setup Time from SCL SCL Low Timeout (Note 1) VDD = 2.7V to 5.5V, THM falling VDD = 2.7V to 5.5V, THM falling VDD = 2.7V to 5.5V, THM falling VDD = 2.7V to 5.5V, THM falling All four comparators, VDD = 2.7V to 5.5V 89.5 73.5 21.5 3.5 91 75 23 5 50 92.5 76.5 24.5 6.5 % of VDD % of VDD % of VDD % of VDD mV 0 < VIMAX < VREF 0 < VVMAX < VREF VIMAX = 0.8V, ChargeCurrent () = 0x1F80 4.75 0 5 MAXIMUM CHARGE-CURRENT SETTING 5.25 VREF 1 A/V V A CONDITIONS PDS and PDL are unloaded MIN 4 TYP 10 MAX 16 UNITS s
MAX1535A
MAXIMUM CHARGE-VOLTAGE SETTING VMAX = 2V, ChargeVoltage () = 0x4B00 4.95 0 5.0 5.05 VREF 1 V/V V A
SMBus INTERFACE LEVEL SPECIFICATIONS (VDD = 2.7V TO 5.5V) VDD = 2.7V to 5.5V VDD = 2.7V to 5.5V VDD = 2.7V to 5.5V VSDA = 0.4V I INT = 1mA 10 4.7 4.7 4 4 300 250 25 35 2.1 -1 6 1 25 200 100 +1 0.8 V V A mA A mV kHz s s s s ns ns ms
INT Output High Leakage Current V INT = 5.5V SMBus TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V)
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5
Highly Integrated Level 2 SMBus Battery Charger MAX1535A
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VDD = 3.3V, ACIN = PGND = GND, LDO = DLOV, VMAX = IMAX = REF, CLDO = 1F, CDHIV = 0.1F, CREF = 1F, TA = 0C to +85C. Typical values are at TA = +25C, unless otherwise noted.)
PARAMETER SCL Low Period SCL High Period Maximum Charging Period Without a ChargeVoltage() or ChargeCurrent() Command CONDITIONS MIN 4.7 4 140 175 210 TYP MAX UNITS s s s
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1. VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VDD = 3.3V, ACIN = PGND = GND, LDO = DLOV, VMAX = IMAX = REF, CLDO = 1F, CDHIV = 0.1F, CREF = 1F, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER CHARGE-VOLTAGE REGULATION ChargeVoltage() = 0x41A0 and 0x3130 Charge-Voltage Accuracy ChargeVoltage() = 0x20D0 ChargeVoltage() = 0x1060 ChargeVoltage() = 0x41A0 Full-Charge Voltage ChargeVoltage() = 0x3130 ChargeVoltage() = 0x20D0 ChargeVoltage() = 0x1060 CHARGE-CURRENT REGULATION CSIP-to-CSIN Full-Scale CurrentSense Voltage Compliance Current Accuracy Charge Current BATT/CSIP/CSIN Input Voltage Range VCSIP = VCSIN = 12V CSIP/CSIN Input Current INPUT-CURRENT REGULATION CSSP-to-CSSN Full-Scale Current-Sense Voltage VDCIN = 18V 10m sense resistor (R1 in Figure 1) between CSSP and CSSN; InputCurrent() = 0x1580 (11.008A) Input Current-Limit Accuracy 10m sense resistor (R1 in Figure 1) between CSSP and CSSN; InputCurrent() = 0x1000 (8.192A) 10m sense resistor (R1 in Figure 1) between CSSP and CSSN; InputCurrent() = 0x0800 (4.096A) 99 -10 VBATT = 12V 10m sense resistor (R2 in Figure 1) between CSIP and CSIN; ChargeCurrent() = 0x1F80 10m sense resistor (R2 in Figure 1) between CSIP and CSIN; ChargeCurrent() = 0x1F80 72.58 -10 7.258 0 88.70 +10 8.870 19 800 mV % A V A -1.6 -1.6 -1.8 16.532 12.390 8.266 4.116 +1.6 +1.6 +1.8 17.068 12.794 8.534 4.268 V % CONDITIONS MIN TYP MAX UNITS
121 +10
mV
-8
+8
%
-10
+10
6
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Highly Integrated Level 2 SMBus Battery Charger
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VDD = 3.3V, ACIN = PGND = GND, LDO = DLOV, VMAX = IMAX = REF, CLDO = 1F, CDHIV = 0.1F, CREF = 1F, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER CSSP/CSSN Input Voltage Range CSSP/CSSN Input Current DCIN Input Voltage Range DCIN Undervoltage Lockout Trip Point DCIN Quiescent Current BATT Input Current LDO Output Voltage LDO Load Regulation LDO Undervoltage Lockout Trip Point VDD Range VDD Quiescent Current REFERENCE REF Output Voltage REF Undervoltage Lockout Trip Point TRIP POINTS BATT POWER_FAIL Threshold BATT POWER_FAIL Threshold Hysteresis ACIN Threshold ACIN Threshold Hysteresis SWITCHING REGULATOR Off-Time DLOV Supply Current Battery Undervoltage Charge Current DHIV Output Voltage DHIV Sink Current DHI On-Resistance Low DHI On-Resistance High DLO On-Resistance High DLO On-Resistance Low ERROR AMPLIFIERS GMV Transconductance VDHI = VDHIV, IDHI = -10mA VDHI = VSRC, IDHI = 10mA VDLOV = 4.5V, IDLO = 100mA VDLOV = 4.5V, IDLO = -100mA ChargeVoltage() = 0x41A0, VBATT = 16.8V 0.0625 VBATT = 16.0, VDCIN = 21.0 VBATT = 19.0, VDCIN = 21.0 ChargerMode() = 0x0001 VBATT = 2.6V per cell With respect to SRC 64 -4.4 10 7 3 7 3 0.2500 540 230 660 310 10 192 -5.5 ns A mA V mA A/mV ACIN rising VDCIN falling 60 90 1.966 5 160 310 2.129 35 mV mV V mV VDCIN < 6V, VDD = 5.5V, VSCL = VSDA = 5.5V 0 < IREF < 500A REF falling 4.035 DCIN falling DCIN rising 8V < VDCIN < 28V VBATT = 2V to 19V, VDCIN > VBATT + 0.3V 8V < VDCIN < 28V, no load 0 < ILDO < 10mA VDCIN = 8V 3.00 2.7 5.15 VCSSP = VCSSN = VDCIN > 8.0V 8 7.0 7.85 8 800 5.65 100 5.35 5.5 27 4.157 3.9 SUPPLY AND LINEAR REGULATOR 28 V V mA A V mV V V A V V CONDITIONS MIN 8 TYP MAX 28 800 UNITS V A
MAX1535A
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Highly Integrated Level 2 SMBus Battery Charger MAX1535A
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VDD = 3.3V, ACIN = PGND = GND, LDO = DLOV, VMAX = IMAX = REF, CLDO = 1F, CDHIV = 0.1F, CREF = 1F, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER GMI Transconductance GMS Transconductance CCI Clamp Voltage CCV Clamp Voltage CCS Clamp Voltage ACOK ACOK Input Voltage Range ACOK Sink Current PDS, PDL SWITCH CONTROL PDS Switch Turn-Off Threshold PDL Switch Turn-On Threshold PDS Output Low Voltage, PDS Below SRC PDS Turn-On Current PDS Turn-Off Current PDL Turn-On Resistance PDL Turn-Off Current PDL and PDS Transition Delay Time PDL-to-PDS Switchover Time in Relearn Mode VMAX Input Voltage Range VMAX to VBATT Ratio VVMAX = 2V, ChargeVoltage() = 0x4B00 MAXIMUM CHARGE-CURRENT SETTING IMAX Input Voltage Range IMAX to ICHARGE Ratio THERMISTOR COMPARATOR Thermistor Overrange Threshold Thermistor Cold Threshold Thermistor Hot Threshold VDD = 2.7V to 5.5V, THM falling VDD = 2.7V to 5.5V, THM falling VDD = 2.7V to 5.5V, THM falling 89.5 73.5 21.5 3.5 92.5 76.5 24.5 6.5 0.8 2.15 6 200 % of VDD % of VDD % of VDD % of VDD V V mA mV VIMAX = 0.8V, ChargeCurrent() = 0x1F80 DCIN with respect to BATT, DCIN falling DCIN with respect to BATT, DCIN falling IPDS = 0 PDS = SRC VPDS = VSRC - 2V, VDCIN = 16V PDL = GND VCSSN - VPDL = 1.5V PDS and PDL are unloaded PDS and PDL are unloaded 40 40 8 6 10 40 6 4 4 15 16 160 160 160 12 mV mV V mA mA k mA s s V ACOK = 0.4V, ACIN = 1.5V 0 1 28 V mA CONDITIONS ChargeCurrent() = 0x1F80, VCSIP - VCSIN = 80.64mV InputCurrent() = 0x1580, VCSSP - VCSSN = 110.08mV 0.25V < VCCI < 2.0V 0.25V < VCCV < 2.0V 0.25V < VCCS < 2.0V MIN 0.5 0.5 140 140 140 TYP MAX 2 2 600 600 600 UNITS A/mV A/mV mV mV mV
MAXIMUM CHARGE-VOLTAGE SETTING 0 4.9 0 4.5 VREF 5.1 VREF 5.5 V V/V V A/V
Thermistor Underrange Threshold VDD = 2.7V to 5.5V, THM falling SMBus INTERFACE LEVEL SPECIFICATIONS (VDD = 2.7V TO 5.5V) SDA/SCL Input Low Voltage SDA/SCL Input High Voltage SDA, INT Output Sink Current INT Output Low Voltage VDD = 2.7V to 5.5V VDD = 2.7V to 5.5V VSDA = 0.4V I INT = 1mA
8
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Highly Integrated Level 2 SMBus Battery Charger
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1. VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VDD = 3.3V, ACIN = PGND = GND, LDO = DLOV, VMAX = IMAX = REF, CLDO = 1F, CDHIV = 0.1F, CREF = 1F, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER CONDITIONS SMBus TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V) SMBus Frequency SMBus Free Time Start Condition Setup Time from SCL Start Condition Hold Time from SCL Stop Condition Setup Time from SCL SDA Hold Time from SCL SDA Setup Time from SCL SCL Low Timeout SCL Low Period SCL High Period Maximum Charging Period Without a ChargeVoltage() or ChargeCurrent() Command (Note 1) MIN 10 4.7 4.7 4 4 300 250 25 4.7 4 130 220 35 TYP MAX 100 UNITS kHz s s s s ns ns ms s s s
MAX1535A
Note 1: Devices participating in a transfer time out when any clock low exceeds the 25ms minimum timeout period. Devices that have detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms). Note 2: Specifications to -40C are guaranteed by design, not production tested.
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Highly Integrated Level 2 SMBus Battery Charger MAX1535A
Typical Operating Characteristics
(Circuit of Figure 1, VDCIN = 20V, TA = +25C, unless otherwise noted.)
TRANSIENT RESPONSE (BATTERY REMOVAL AND INSERTION)
MAX1535 toc01
LOAD SWITCH CONTROL (ADAPTER INSERTION)
MAX1535 toc02
SYSTEM LOAD TRANSIENT
MAX1535 toc03
16.8VDC A
A 0V B C C C B
A 0V
C C B
B
B C 0V C B 0V 0V D 0V A: B: C: D: 200s/div ADAPTER INPUT VOLTAGE, 20V/div VCSSN, 20V/div VPDS, 20V/div VPDL, 20V/div A: B: C: D: E: F: 400s/div VBATT, 500mV/div, AC-COUPLED VCCS, 500mV/div VCCI, 500mV/div AC ADAPTER CURRENT, 5A/div SYSTEM LOAD, 5A/div CHARGE CURRENT, 5A/div B
D 0V E 0V F
BATT INSERTED BATT REMOVED A: B: C: D: 4ms/div BATTERY VOLTAGE, 500mV/div, AC-COUPLED VCCV, 500mV/div VCCI, 500mV/div CHARGE CURRENT, 2A/div
D 0V
LDO LOAD REGULATION (VIN = 20V)
MAX1535 toc04
LDO LINE REGULATION
MAX1535 toc05
REF LOAD REGULATION
MAX1535 toc06
0.4 0.2 LDO VOLTAGE ERROR (%) 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2 4 6 8
0.010 0.008 LDO VOLTAGE ERROR (%) 0.006 0.004 0.002 0 -0.002 -0.004 -0.006 -0.008 -0.010
0
REF VOLTAGE ERROR (%) 8 12 16 20 24 28
-0.02
-0.04
-0.06
-0.08
-0.10 0 100 200 300 400 500 INPUT VOLTAGE (V) REF LOAD CURRENT (A)
10
LDO CURRENT (mA)
REF VOLTAGE ERROR vs. TEMPERATURE
MAX1535 toc10
EFFICIENCY vs. CHARGE CURRENT (CONSTANT-VOLTAGE MODE)
MAX1535 toc08
0.02 0 REF VOLTAGE ERROR (%) -0.02 -0.04 -0.06 -0.08 -0.10 -40 -20 0 20 40 60 80
100 90 EFFICIENCY (%) 80 70 60 50 40 VCHARGE = 8.4V VCHARGE = 12.6V VCHARGE = 16.8V
100
0
2
4 CHARGE CURRENT (A)
6
8
TEMPERATURE (C)
10
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Highly Integrated Level 2 SMBus Battery Charger MAX1535A
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VDCIN = 20V, TA = +25C, unless otherwise noted.)
EFFICIENCY vs. CHARGE CURRENT (CONSTANT-CURRENT MODE)
MAX1535 toc09
FREQUENCY vs. VIN - VBATT
MAX1535 toc10
CHARGE-VOLTAGE ACCURACY
MAX1535 toc11
100 90 EFFICIENCY (%) 80 70 60 50 40 0 2 4 CHARGE CURRENT (A) 6 8 VCHARGE = 8.4V VCHARGE = 12.6V VCHARGE = 16.8V
600 500 FREQUENCY (kHz) 400 300 200 100 0 0 4 8 12 16
1.0
CHARGE VOLTAGE ERROR (%)
0.5
0
-0.5
-1.0 20 4 8 12 16 20 VIN - VBATT (V) CHARGEVOLTAGE() CODE (V)
CHARGE-CURRENT ACCURACY
MAX1535 toc12
INPUT-CURRENT ACCURACY
MAX1535 toc13
INPUT/CHARGE CURRENT vs. SYSTEM LOAD CURRENT
CHARGECURRENT() = 4A INPUTCURRENT() = 6A INPUT/CHARGE CURRENT (A) 6 INPUT CURRENT 4
MAX1535 toc14
5.0
2.5
8
CHARGE-CURRENT ERROR (%)
2.5
INPUT CURRENT ERROR (%)
0
0
-2.5
-2.5
-5.0
2 CHARGE CURRENT
-5.0 0 2 4 6 8 CHARGECURRENT() SETTING (A)
-7.5 0 2 4 6 8 10 12 INPUTCURRENT() SETTING (A)
0 0 2 4 6 8 SYSTEM LOAD CURRENT (A)
MAXIMUM CHARGE VOLTAGE vs. IMAX
MAX1535 toc15
MAXIMUM CHARGE CURRENT vs. VMAX
MAX1535 toc16
10 MAXIMUM CHARGE VOLTAGE (V)
20 MAXIMUM CHARGE CURRENT (A)
8
16
6
12
4 SLOPE 5V/V 2
8 SLOPE 5A/V 4
0 0 1 2 3 4 5 IMAX VOLTAGE (V)
0 0 1 2 3 4 5 VMAX VOLTAGE (V)
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11
Highly Integrated Level 2 SMBus Battery Charger MAX1535A
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME DCIN LDO ACIN REF GND CCS CCI CCV VMAX IMAX DAC VDD THM SDA SCL INT I.C. GND BATT CSIN CSIP PGND DLO DLOV DHIV DHI SRC CSSN CSSP PDL PDS ACOK FUNCTION DC Supply Voltage Input. Bypass DCIN to power ground (PGND) with a 1F ceramic capacitor. 5.4V Linear-Regulator Output. The linear regulator powers the internal circuitry of the device. The input of the linear regulator is supplied from DCIN. Bypass LDO with a 1F ceramic capacitor to GND. AC Adapter Detect Input. This uncommitted comparator input can be used to detect if the AC adapter voltage is available for charging. 4.096V (Typical) Reference Voltage Output. Bypass REF with a 1F ceramic capacitor to GND. Analog Ground Input Current-Limit Regulation Loop Compensation Point. Connect a 0.01F capacitor to GND. Charge-Current Regulation Loop Compensation Point. Connect a 0.01F capacitor to GND. Charge-Voltage Regulation Loop Compensation Point. Connect a 20k resistor in series with a 0.01F capacitor to GND. Analog Control Input for Setting the Maximum Charge Voltage. The maximum charge voltage can never go above the limit set by VMAX. The ratio of maximum charge voltage to VMAX voltage is 5V/V. Analog Control Input for Setting the Maximum Charge Current. The maximum charge current can never go above the limit set by IMAX. The ratio of maximum charge current to IMAX voltage is 5A/V. DAC Voltage Output. Bypass DAC with a 0.1F ceramic capacitor to GND. Logic Circuitry Supply Voltage Input. The voltage range of VDD is 2.7V to 5.5V. Thermistor Voltage Input SMBus Data Input/Output. SDA is an open-drain output. An external pullup resistor is needed. SMBus Clock Input. An external pullup resistor is needed. Interrupt Output. INT is an open-drain output. An external pullup resistor is needed. Internally Connected Pin. Leave it unconnected or connect it to ground. Analog Ground Battery Voltage Input Negative Input to the Charge Current-Sense Amplifier Positive Input to the Charge Current-Sense Amplifier. Connect a 10m current-sense resistor from CSIP to CSIN. Power Ground Low-Side Power MOSFET Gate Driver Output. Connect DLO to the gate of the low-side N-channel MOSFET. Low-Side Gate Driver Supply. Bypass DLOV with a 0.1F ceramic capacitor to PGND. High-Side Gate Driver Supply. Bypass DHIV with a 0.1F ceramic capacitor to CSSN. High-Side Power MOSFET Gate Driver Output. Connect DHI to the gate of the high-side P-channel MOSFET. Source Connection for PDS and PDL Switch Drivers Negative Input to the Input Current-Limit Sense Amplifier Positive Input to the Input Current-Limit Sense Amplifier. Connect a 10m current-sense resistor from CSSP to CSSN. System Load P-Channel MOSFET Switch Driver Output. When the MAX1535A is powered down, the PDL output is pulled to ground through an internal 100k resistor. Power Source P-Channel MOSFET Switch Driver Output. When the MAX1535A is powered down, the PDS output is pulled to SRC through an internal 1M resistor. AC Detect Output. This high-voltage open-drain output is low impedance when ACIN is less than REF/2. The ACOK output remains low impedance when the MAX1535A is powered down.
12
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Highly Integrated Level 2 SMBus Battery Charger
Detailed Description
The MAX1535A includes all the functions necessary to charge Li+, NiMH, and NiCd smart batteries. A highefficiency, synchronous-rectified, step-down DC-to-DC converter is used to implement a precision constantcurrent, constant-voltage charger with input current limiting. The DC-to-DC converter uses an external P-channel MOSFET as the buck switch and an external N-channel MOSFET as the synchronous rectifier to convert the input voltage to the required charge current and voltage. The charge current and input current-limit sense amplifiers have low input-offset errors and can use small-value sense resistors. The MAX1535A features a voltage-regulation loop (CCV) and two current-regulation loops (CCI and CCS). The loops operate independently of each other. The CCV voltage-regulation loop monitors BATT to ensure that its voltage never exceeds the voltage set by the ChargeVoltage() command. The CCI battery currentregulation loop monitors current delivered to BATT to ensure that it never exceeds the current limit set by the ChargeCurrent() command. The charge current-regulation loop is in control as long as the BATT voltage is below the set point. When the BATT voltage reaches its set point, the voltage-regulation loop takes control and maintains the battery voltage at the set point. A third loop (CCS) takes control and reduces the charge current when the sum of the system load and the input current to the charger exceeds the power-source current limit set by the InputCurrent() command. The MAX1535A also allows the user to clamp the programmed charge current and charge voltage. This feature effectively avoids damage to the battery if the charger was programmed with invalid data. Based on the presence or absence of the AC adapter, the MAX1535A automatically selects the appropriate source for supplying power to the system. A P-channel load switch controlled from the PDL output and a similar P-channel source switch controlled from the PDS output are used to implement this function. The MAX1535A can be programmed by a microcontroller (C) to perform a relearning, or conditioning, cycle in which the battery is isolated from the charger and completely discharged through the system load. When the battery reaches 100% depth of discharge, it is recharged to full capacity (contact the battery-pack manufacturers for the 100% depth of discharge threshold). The circuit shown in Figure 1 demonstrates a typical application for smart-battery systems.
Setting Charge Voltage
The SMBus specification allows for a 16-bit ChargeVoltage() command that translates to a 1mV LSB and a 65.535V full-scale voltage; therefore, the ChargeVoltage() code corresponds to the output voltage in millivolts. The MAX1535A ignores the first 4 LSBs, and uses the next 11 bits to control the voltage DAC. The charge voltage range of the MAX1535A is 0 to 19.200V. All codes requesting charge voltage greater than 19.200V result in a voltage setting of 19.200V. All codes requesting charge voltage below 1.024V result in a voltage set point of zero, which terminates charging. The VMAX pin can be used to set an upper limit to the charge voltage. This feature supercedes the value set with the ChargeVoltage() command when charge voltage is greater than VCHARGE_MAX. The voltage range of VMAX is from 0 to VREF. The maximum charge voltage can be related to the voltage on VMAX using the following equation: VCHARGE _ MAX = 5V x VVMAX V
MAX1535A
where VVMAX is the voltage on the VMAX pin.
Setting Charge Current
The SMBus specification allows for a 16-bit ChargeCurrent() command that translates to a 1mA LSB and a 65.535A full-scale current using a 10m current-sense resistor (R2 in Figure 1). Equivalently, the ChargeCurrent() value sets the voltage across CSIP and CSIN inputs in 10V per LSB increment. The MAX1535A ignores the first 7 LSBs and uses the next 6 bits to control the current DAC. The charge-current range of the MAX1535A is 0 to 8.064A using a 10m current-sense resistor. All codes requesting charge current above 8.064A result in a current setting of 8.064A. All codes requesting charge current between 1mA to 128mA result in a current setting of 128mA. The default charge-current setting at power-on reset (POR) is also 128mA. The IMAX pin can be used to set an upper limit to the charge current. This feature supercedes the value set with the ChargeCurrent() command when charge current is greater than ICHARGE_MAX. The voltage range of IMAX is from 0 to VREF. The maximum charge current can be related to the voltage on IMAX using the following equation: ICHARGE _ MAX = 5A x VIMAX V
where VIMAX is the voltage on the IMAX pin.
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Highly Integrated Level 2 SMBus Battery Charger MAX1535A
P4 (OPTIONAL) P3 AC ADAPTER INPUT 8.5V TO 24V R1 0.01 TO SYSTEM LOAD C1 22F C11 0.1F C2 22F
SRC R3 365k 1% D1 C5 1F PDS DCIN R4 49.9k 1% C6 1F
CSSP
CSSN DHIV PDL LDO
P2
C7 1F MAX1535A ACIN DLOV
R11 33 C8 1F P1
VCC R5 1M INPUT ACOK CCS CCI CCV R6 20k C14 0.01F CSIP DLO PGND DHI
C12 0.01F C13 0.01F
N1 L1 4.3H
HOST
R2 0.01 VDD R7 10k R8 10k R9 10k R10 10k THM SDA SCL GPIO INT IMAX DAC C10 0.1F REF C9 1F GND R14 137k 1% R15 49.9k 1% VMAX R13 100k 1% SMART BATTERY VDD CSIN BATT R12 14.7k 1% C3 22F C4 22F BATT+
SCL SDA TEMP GND
SCL SDA TEMP BATT-
PGND
GND
Figure 1. Standard Application Circuit 14 ______________________________________________________________________________________
Highly Integrated Level 2 SMBus Battery Charger
Table 1. Summary of Operating States
INPUT CONDITIONS DCIN THM BATT VDD OPERATING STATES AC PRESENT VDCIN > 7.5V X X X POWER FAIL VDCIN < VBATT + 0.3V X VBATT > VDCIN 0.3V X BATTERY X VTHM < 0.91 x VDD X X BATT UNDERVOLTAGE X X VBATT < 2.5V X VDD UNDERVOLTAGE X X X VDD < 2.5V
MAX1535A
X = Don't care.
Setting Input-Current Limit
The total input current, from a wall cube or other DC source, is the sum of the system supply current and the current required by the charger. The MAX1535A reduces the source current by decreasing the maximum charge current when the input current exceeds the set input current limit. This technique does not truly limit the input current. As the system supply current rises, the available charge current drops proportionally to zero. Thereafter, the total input current can increase without limit. An internal amplifier compares the differential voltage between CSSP and CSSN to a scaled voltage set by the InputCurrent() command over the SMBus. The total input current is the sum of the device supply current, the charger input current, and the system load current. The device supply current is minimal (6mA, max) in comparison to the charger current and system load. The total input current can be estimated as follows: IINPUT = ILOAD + (ICHARGE x VBATT ) / (VIN x )
carefully calculate its power rating. Take into account variations in the system's load current and the overall accuracy of the sense amplifier. Note that the voltage drop across R1 contributes additional power loss, which reduces efficiency. System currents normally fluctuate as portions of the system are powered up or put to sleep. Without inputcurrent regulation, the input source must be able to deliver the maximum system current and the maximum charger-input current. By using the input-current-limit circuit, the output-current capability of the AC wall adapter can be lowered, reducing system cost.
LDO Regulator
An integrated low dropout (LDO) linear regulator provides a 5.4V supply derived from DCIN, which can deliver at least 10mA of load current. The LDO powers the gate driver of the low-side N-channel MOSFET in the DC-to-DC converter. See the MOSFET Drivers section. The LDO also biases the 4.096V reference and most of the control circuitry. Bypass LDO to GND with a 1F ceramic capacitor.
[
]
VDD Supply
where is the efficiency of the DC-to-DC converter (typically 85% to 95%). The MAX1535A allows for a 16-bit InputCurrent() command that translates to a 1mA LSB and a 65.535A fullscale current using a 10m current-sense resistor (R1 in Figure 1). Equivalently, the InputCurrent() value sets the voltage across CSSP and CSSN inputs in 10V per LSB increments. The MAX1535A ignores the first 7 LSBs and uses the next 6 bits to control the input-current DAC. The input-current range of the MAX1535A is from 256mA to 11.004A. All codes requesting input current above 11.004A result in an input-current setting of 11.004A. All codes requesting input current between 1mA to 256mA result in an input-current setting of 256mA. The default input-current-limit setting at POR is 256mA. When choosing the current-sense resistor R1, The VDD input provides power to the SMBus interface and the thermistor comparators. Connect VDD to LDO, or apply an external supply to VDD to keep the SMBus interface active while the supply to DCIN is removed.
Operating Conditions
Table 1 is a summary of the following four MAX1535A operating states: * AC present. When DCIN is greater than 7.5V, the AC adapter is considered to be present. In this condition, both the LDO and REF function properly and battery charging is allowed. The AC_PRESENT bit (bit 15) in the ChargerStatus() register is set to 1. * Power fail. When DCIN is less than BATT + 0.3V, the part is in the power-fail state since the charger does not have enough input voltage to charge the battery.
15
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Highly Integrated Level 2 SMBus Battery Charger MAX1535A
VDD IMAX SRC
THO DACI THC SRC-10V DACS THH SRC
1M PDS
MAX1535A
THU DACV 1M PDL
SMBus THM SDA SCL INT LOGIC AND DEAD TIME
BATT
DCIN DCIN LDO LINEAR REGULATOR GMS ACIN LEVEL SHIFTER ACOK
VMAX CSSP CSSN CSIP LEVEL SHIFTER CSIN
REFERENCE
REF
REF/2
ENABLE CCS CSI GMI DC-DC CONVERTER DH
SRC
DHI
DHIV DLOV
CCI BATT GMV
LVC
LVC
DL
DLO
PGND
DCIN
BATT
GND
CCV
Figure 2. System Functional Diagram 16 ______________________________________________________________________________________
Highly Integrated Level 2 SMBus Battery Charger
In power fail, PDS turns off the input P-channel MOSFET switch and the POWER_FAIL bit (bit 13) in the ChargerStatus() register is set to 1. * Battery present. When THM is less than 91% of VDD, the battery is considered to be present. The MAX1535A uses the THM pin to detect whether a battery is connected to the charger. When the battery is present, the BATTERY_PRESENT bit (bit 14) in the ChargerStatus() register is set to 1. * Battery undervoltage. When BATT is less than 2.5V, the battery is considered to be in an undervoltage state. This condition causes the charger to reduce its current compliance to 128mA. The content of the ChargeCurrent() register is unaffected. When the BATT voltage exceeds 2.7V, normal charging resumes. ChargeVoltage() is unaffected and can be set as low as 1.024V. * VDD undervoltage. When VDD is less than 2.5V, the VDD supply is considered to be in an undervoltage state. The SMBus interface does not respond to commands. Coming out of the undervoltage condition, the part is in its POR state. No charging occurs when VDD is in the undervoltage state.
MAX1535A
SMBus Interface
The MAX1535A receives control inputs from the SMBus interface. The serial interface complies with the SMBus protocols as documented in System Management Bus Specification V1.1 and can be downloaded from www.sbs-forum.org. The charger functionality complies with Intel/Duracell smart charger specifications for a level 2 charger, as well as supporting input current limit and power source selection functions. The MAX1535A uses the SMBus Read-Word and WriteWord protocols (Figure 3) to communicate with the bat-
a) Write-Word Format
S SLAVE ADDRESS 7 bits MSB LSB Preset to 0b0001001 W 1b 0 ACK 1b 0 COMMAND BYTE 8 bits MSB LSB ChargerMode() = 0x12 ChargeCurrent() = 0x14 ChargeVoltage() = 0x15 AlarmWarning() = 0x16 InputCurrent() = 0x3F ACK 1b 0 D7 LOW DATA BYTE 8 bits MSB LSB D0 ACK 1b 0 D15 HIGH DATA BYTE 8 bits MSB LSB D8 ACK 1b 0 P
b) Read-Word Format
S SLAVE W ACK ADDRESS 7 bits MSB LSB Preset to 0b0001001 1b 0 1b 0
COMMAND BYTE 8 bits MSB LSB ChargerSpecInfo() = 0x11 ChargerStatus() = 0x13
ACK S 1b 0
SLAVE ADDRESS 7 bits MSB LSB Preset to 0b0001001
R ACK 1b 1 1b 0 D7
LOW DATA BYTE 8 bits MSB LSB D0
ACK 1b 0
HIGH DATA BYTE 8 bits MSB LSB D15 D8
NACK P 1b 1
LEGEND: S = START CONDITION or REPEATED START CONDITION ACK = ACKNOWLEDGE (LOGIC LOW) W = WRITE BIT (LOGIC LOW) MASTER TO SLAVE SLAVE TO MASTER
P = Stop Condition NACK = NOT ACKNOWLEDGE (LOGIC HIGH) R = READ BIT (LOGIC HIGH)
Figure 3. SMBus a) Write-Word and b) Read-Word Protocols ______________________________________________________________________________________ 17
Highly Integrated Level 2 SMBus Battery Charger MAX1535A
A tLOW B tHIGH C D E F G H I J K L M
SMBCLK
SMBDATA
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tHD:DAT
tSU:STO tBUF J = ACKNOWLEDGE CLOCKED INTO MASTER K = ACKNOWLEDGE CLOCK PULSE L = STOP CONDITION, DATA EXECUTED BY SLAVE M = NEW START CONDITION
A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO SLAVE H = LSB OF DATA CLOCKED INTO SLAVE I = SLAVE PULLS SMBDATA LINE LOW
Figure 4. SMBus Write Timing
A tLOW
B tHIGH
C
D
E
F
G
H
I
J
K
SMBCLK
SMBDATA
tSU:STA tHD:STA A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE
tSU:DAT
tHD:DAT E = SLAVE PULLS SMBDATA LINE LOW F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO MASTER H = LSB OF DATA CLOCKED INTO MASTER
tSU:DAT
tSU:STO
tBUF
I = ACKNOWLEDGE CLOCK PULSE J = STOP CONDITION K = NEW START CONDITION
Figure 5. SMBus Read Timing
tery being charged, as well as with any host system that monitors the battery-to-charger communications as a level 2 SMBus charger. The MAX1535A is an SMBus slave device and does not initiate communication on the bus. It responds to the 7-bit address 0b0001001. In addition, the MAX1535A has two identification (ID) registers: a 16-bit device ID register (0x0006), and a 16-bit manufacturer ID register (0x004D). The data input SDA and clock input SCL pins have Schmitt-trigger inputs that can accommodate slow edges; however, the rising and falling edges should still be faster than 1s and 300ns, respectively.
18
Communication starts with the master signaling the beginning of a transmission with a START condition, which is a high-to-low transition on SDA, while SCL is high. When the master has finished communicating with the slave, the master issues a STOP condition, which is a low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figures 4 and 5 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and data byte are transmitted between the START and STOP conditions. The SDA state is allowed to change only while SCL is low, except for the START
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Highly Integrated Level 2 SMBus Battery Charger
and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the MAX1535A since either the master or the slave acknowledges the receipt of the correct byte during the ninth clock. The MAX1535A supports the charger commands as described in Tables 2-9. ChargerStatus() The ChargerStatus() command uses the Read-Word protocol (Figure 3). The command code for ChargerStatus() is 0x13 (0b00010011). Table 5 describes the functions of the data bits (D0-D15). Bit 0 refers to the D0 bit in the Read-Word protocol. The ChargerStatus() command returns information about thermistor impedance and the MAX1535A's internal state. The latched bits, THERMISTOR_HOT and ALARM_INHIBITED, are cleared whenever BATTERY_ PRESENT = 0 or ChargerMode() is written with POR_RESET = 1. The ALARM_INHIBITED status bit can also be cleared by writing a new charge current or charge voltage. ChargeCurrent() (POR: 0x0080) The ChargeCurrent() command uses the Write-Word protocol (Figure 3). The command code for ChargeCurrent() is 0x14 (0b00010100). The 16-bit binary number formed by D15-D0 represents the charge-current set point in milliamps. However, the resolution of the MAX1535A is 128mA in setting the charge current; bits D0-D6 are ignored as shown in Table 6. The D13, D14, and D15 bits are also ignored. Figure 6 shows the mapping between the charge-current set point and the ChargeCurrent() code. All codes requesting charge current above 8.064A result in a current overrange, limiting the charging current to 8.064A. All codes requesting charge current between 1mA to 128mA result in a current setting of 128mA. A 10m current-sense resistor (R2 in Figure 1) is required to achieve the correct code/current scaling.
MAX1535A
Battery-Charger Commands
The MAX1535A supports seven battery charger commands that use either Write-Word or Read-Word protocols, as summarized in Table 2. ChargerSpec() The ChargerSpec() command uses the Read-Word protocol (Figure 3). The command code for ChargerSpec() is 0x11(0b00010001). Table 3 lists the functions of the data bits (D0-D15). Bit 0 refers to the D0 bit in the Read-Word protocol. The MAX1535A complies with Level 2 SmartBattery Charger Specification Revision 1.1; therefore, the ChargerSpec() command returns 0x0002. ChargerMode() The ChargerMode() command uses the Write-Word protocol (Figure 3). The command code for ChargerMode() is 0x12 (0b00010010). Table 4 lists the functions of the data bits (D0-D15). Bit 0 refers to the D0 bit in the Write-Word protocol. To charge a battery that has a thermistor impedance in the HOT range (i.e., THERMISTOR_HOT = 1 and THERMISTOR_UR = 0), the host must use the ChargerMode() command to clear HOT_STOP after the battery is inserted. The HOT_STOP bit returns to its default power-up condition (1) whenever the battery is removed.
Table 2. Battery-Charger Command Summary
COMMAND 0x11 0x12 0x13 0x14 0x15 0x16 0x3F 0xFE 0xFF COMMAND NAME ChargerSpec() ChargerMode() ChargerStatus() ChargeCurrent() ChargeVoltage() AlarmWarning() InputCurrent() DeviceID() ManufacturerID() READ/WRITE Read Only Write Only Read Only Write Only Write Only Write Only Write Only Read Only Read Only DESCRIPTION Charger specification Charger mode Charger status Charge-current setting Charge-voltage setting Alarm warning Input current-limit setting Device ID Manufacturer ID POR STATE 0x0002 N/A N/A 0x0080 0x4B00 N/A 0x0080 0x0006 0x004D STATUS BITS AFFECTED N/A CHARGE_INHIBITED, ALARM_INHIBITED, THERMISTOR_HOT N/A CURRENT_NOT_REG, CURRENT_OR VOLTAGE_NOT_REG, VOLTAGE_OR N/A CURRENT_NOT_REG N/A N/A
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19
Highly Integrated Level 2 SMBus Battery Charger MAX1535A
Table 3. ChargerSpec()
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BIT NAME CHARGER_SPEC CHARGER_SPEC CHARGER_SPEC CHARGER_SPEC SELECTOR_SUPPORT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Returns a zero for version 1.1 Returns a 1 for version 1.1 Returns a zero for version 1.1 Returns a zero for version 1.1 Returns a zero, indicating no smart-battery selector functionality Returns a zero Returns a zero Returns a zero Returns a zero Returns a zero Returns a zero Returns a zero Returns a zero Returns a zero Returns a zero Returns a zero DESCRIPTION
Command: 0x11
The default charge-current setting at POR is 128mA. Thus, the first time a MAX1535A powers up, the charge current is regulated at 128mA. Anytime the battery is removed, the ChargeCurrent() register returns to its POR state. ChargeVoltage() (POR: 0x4B00) The ChargeVoltage() command uses the Write-Word protocol (Figure 3). The command code for ChargeVoltage() is 0x15 (0b00010101). The 16-bit binary number formed by D15-D0 represents the charge-voltage set point in millivolts. However, the resolution of the MAX1535A is 16mV in setting the charge voltage; the D0-D3 bits are ignored as shown in Table 7. The D15 bit is also ignored. Figure 7 shows the mapping between the charge-voltage set point and the ChargeVoltage() code. All codes requesting charge voltage greater than 19.200V result in a voltage overrange, limiting the charge voltage to 19.200V. All codes requesting charge voltage below 1024mV result in a voltage set point of zero, which terminates charging. The default charge-voltage setting at POR is 19.200V. Thus, the first time a MAX1535A powers up, the charge voltage is regulated at 19.200V. Anytime the battery is removed, the ChargeVoltage() register returns to its POR state.
AlarmWarning() The AlarmWarning() command uses the Write-Word protocol (Figure 3). The command code for AlarmWarning() is 0x16 (0b00010110). AlarmWarning() sets the ALARM_INHIBITED status bit in the MAX1535A if D15, D14, D13, D12, or D11 of the Write-Word protocol equals 1. Table 8 summarizes the AlarmWarning() command's function. The ALARM_INHIBITED status bit remains set until the battery is removed, a ChargerMode() command is written with the POR_RESET bit set, or new ChargeCurrent() and ChargeVoltage() values are written. As long as ALARM_INHIBITED = 1, the MAX1535A switching regulator remains off. InputCurrent() (POR: 0x0080) The InputCurrent() command uses the Write-Word protocol (Figure 3). The command code for InputCurrent() is 0x3F (0b00111111). The 16-bit binary number formed by D15-D0 represents the charge-current set point in milliamps. However, the resolution of the MAX1535A is 256mA in setting the charge current; the D0-D6 bits are ignored as shown in Table 9. The D13, D14, and D15 bits are also ignored. Figure 8 shows the mapping between the input-current set point and the InputCurrent() code. All codes requesting input current greater than 11.004A result in an input-current overrange, limiting the input current to 11.004A. All codes requesting input current between 1mA and 256mA
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Highly Integrated Level 2 SMBus Battery Charger
Table 4. ChargerMode()
BIT 0 1 2 BIT NAME INHIBIT_CHARGE ENABLE_POLLING POR_RESET DESCRIPTION 0* = Allow normal operation; clear the CHG_INHIBITED flip-flop. 1 = Turn off the charger; set the CHG_INHIBITED flip-flop. The CHG_INHIBITED flip-flop is not affected by any other commands. Not implemented 0* = No change. 1 = Change the ChargeVoltage() to 0x4B00 and the ChargeCurrent() to 0x0080; clear the THERMISTOR_HOT and ALARM_INHIBITED flip-flops. 0* = No change. 1 = Set the ChargeCurrent() and ChargeVoltage() to zero even if the INHIBITED_CHARGE bit is zero. 0* = Interrupt on either edge of the AC_PRESENT status bit. 1 = Do not interrupt because of an AC_PRESENT bit change. 0* = Interrupt on either edge of the BATTERY_PRESENT status bit. 1 = Do not interrupt because of a BATTERY_PRESENT bit change. 0* = Interrupt on either edge of the POWER_FAIL status bit. 1 = Do not interrupt because of a POWER_FAIL bit change. Not implemented 0* = When DCIN > BATT + 100mV, PDS pulls low and PDL pulls high. 0 = When DCIN < BATT + 100mV, PDS pulls high and PDL pulls low. 1 = When THM < 91% and DCIN > BATT + 100mV, PDS pulls high and PDL pulls low. 1 = When THM > 91% and DCIN > BATT + 100mV, PDS pulls high and PDL pulls low. Not implemented 0 = The THERMISTOR_HOT status bit does not turn off the charger. 1* = The THERMISTOR_HOT status bit does turn off the charger. THERMISTOR_HOT is reset by either POR_RESET or BATTERY_PRESENT = 0. Not implemented Not implemented Not implemented Not implemented Not implemented
MAX1535A
3
RESET_TO_ZERO
4 5 6 7
AC_PRESENT_MASK BATTERY_PRESENT_MASK POWER_FAIL_MASK --
8
CALIBRATION_ENABLE
9 10 11 12 13 14 15 Command: 0x12
-- HOT_STOP -- -- -- -- --
* Indicates POR state.
result in a current setting of 256mA. A 10m currentsense resistor (R1 in Figure 1) is required to achieve the correct code/current scaling. The default input current-limit setting at POR is 256mA. Thus, the first time a MAX1535A powers up, the input current is limited to 256mA. Anytime the battery is removed, the InputCurrent() register returns to its POR state.
Interrupts and Alert Response Address
The MAX1535A requests an interrupt by pulling the INT pin low. An interrupt is normally requested when there is a change in the state of the ChargerStatus() bits POWER_FAIL (bit 13), BATTERY_PRESENT (bit 14), or AC_PRESENT (bit 15). Therefore, the INT pin pulls low whenever the AC adapter is connected or disconnected, the battery is inserted or removed,
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Highly Integrated Level 2 SMBus Battery Charger MAX1535A
Table 5. ChargerStatus()
BIT 0 1 2 3 4 5 6 BIT NAME CHARGE_INHIBITED MASTER_MODE VOLTAGE_NOT_REG CURRENT_NOT_REG LEVEL_2 LEVEL_3 CURRENT_OR DESCRIPTION 0* = Ready to charge the smart battery. 1 = Charging is inhibited; charge current is 0mA. This status bit returns the value of the CHG_INHIBITED flip-flop. Always returns a zero 0 = Battery voltage is limited at the set point. 1 = Battery voltage is less than the set point. 0 = Battery current is limited at the set point. 1 = Battery current is less than the set point. Always returns a 1 Always returns a zero 0 = The ChargeCurrent() value is valid for the MAX1535A. 1 = The ChargeCurrent() value exceeds the MAX1535A output range, i.e., programmed ChargeCurrent() exceeds 0x1F80. 0 = The ChargeVoltage() value is valid for the MAX1535A. 1 = The ChargeVoltage() value exceeds the MAX1535A output range, i.e., programmed ChargeVoltage() exceeds 0x4B00. 0 = THM is < 91% of VDD. 1 = THM is > 91% of VDD. 0 = THM is < 75% of VDD. 1 = THM is > 75% of VDD. 0 = THM has not dropped to < 23% of VDD. 1 = THM has dropped to < 23% of VDD. THERMISTOR_HOT flip-flop cleared by BATTERY_PRESENT = 0 or writing a 1 into the POR_RESET bit in the ChargerMode() command. 0 = THM is > 5% of VDD. 1 = THM is < 5% of VDD. Returns the state of the ALARM_INHIBITED flip-flop. This flip-flop is set by either a watchdog timeout or by writing an AlarmWarning() command with bits 12, 14, or 15 set. This flip-flop is cleared by BATTERY_PRESENT = 0, or writing a 1 into the POR_RESET bit in the ChargerMode() command, or by receiving successive ChargeVoltage() and ChargeCurrent() commands. 0 = ACIN is above the REF/2 threshold. 1 = ACIN is below the REF/2 threshold. 0 = No battery is present (VTHM > 0.91 x VDD). 1 = Battery is present (VTHM < 0.91 x VDD). 0 = DCIN is below the 7.5V undervoltage threshold. 1 = DCIN is above the 7.5V undervoltage threshold.
7
VOLTAGE_OR
8 9
THERMISTOR_OR THERMISTOR_COLD
10
THERMISTOR_HOT
11
THERMISTOR_UR
12
ALARM_INHIBITED
13 14 15
POWER_FAIL BATTERY_PRESENT AC_PRESENT
Command: 0x13 * Indicates POR state.
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Highly Integrated Level 2 SMBus Battery Charger
Table 6. ChargeCurrent()
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BIT NAME -- -- -- -- -- -- -- Charge Current, DACI 0 Charge Current, DACI 1 Charge Current, DACI 2 Charge Current, DACI 3 Charge Current, DACI 4 Charge Current, DACI 5 -- -- -- DESCRIPTION Not used. Normally a 1mA weight. Not used. Normally a 2mA weight. Not used. Normally a 4mA weight. Not used. Normally an 8mA weight. Not used. Normally a 16mA weight. Not used. Normally a 32mA weight. Not used. Normally a 64mA weight. 0 = Adds 0mA of charger-current compliance. 1 = Adds 128mA of charger-current compliance. 0 = Adds 0mA of charger-current compliance. 1 = Adds 256mA of charger-current compliance. 0 = Adds 0mA of charger-current compliance. 1 = Adds 512mA of charger-current compliance. 0 = Adds 0mA of charger-current compliance. 1 = Adds 1024mA of charger-current compliance. 0 = Adds 0mA of charger-current compliance. 1 = Adds 2048mA of charger-current compliance, 8064mA max. 0 = Adds 0mA of charger-current compliance. 1 = Adds 4096mA of charger-current compliance, 8064mA max. Not used. Normally an 8192mA weight. Not used. Normally a 16384mA weight. Not used. Normally a 32768mA weight.
MAX1535A
Command: 0x14
or the charger goes in or out of dropout. The interrupts from each of the ChargerStatus() bits can be masked by an associated ChargerMode() bit POWER_FAIL_MASK (bit 6), BATTERY_PRESENT_MASK (bit 5), or AC_PRESENT_MASK (bit 4). Interrupts are cleared by sending a command to the AlertResponse() address, 0x19, using a modified Receive-Byte protocol. In this protocol, the devices that set an interrupt try to respond by transmitting their addresses, and the devices with the highest priority or most leading zeros are recognized and cleared. This process is repeated until all devices requesting interrupts are addressed and cleared. The MAX1535A responds to the AlertResponse() address with 0x13, which is its address and a trailing 1.
8064
CHARGE-CURRENT SET POINT (mA)
4096
2048
128 0x0080 0x0800 0x1000 CHARGECURRENT() CODE 0x1F80 0xFFFF
Figure 6. ChargeCurrent() Code to Charge-Current Set Point Mapping (R2 = 10m) ______________________________________________________________________________________ 23
Highly Integrated Level 2 SMBus Battery Charger MAX1535A
Table 7. ChargeVoltage()
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BIT NAME -- -- -- -- Charge Voltage, DACV 0 Charge Voltage, DACV 1 Charge Voltage, DACV 2 Charge Voltage, DACV 3 Charge Voltage, DACV 4 Charge Voltage, DACV 5 Charge Voltage, DACV 6 Charge Voltage, DACV 7 Charge Voltage, DACV 8 Charge Voltage, DACV 9 Charge Voltage, DACV 10 -- DESCRIPTION Not used. Normally a 1mV weight. Not used. Normally a 2mV weight. Not used. Normally a 4mV weight. Not used. Normally an 8mV weight. 0 = Adds 0mV of charge-voltage compliance, 1024mV min. 1 = Adds 16mV of charge-voltage compliance. 0 = Adds 0mV of charge-voltage compliance, 1024mV min. 1 = Adds 32mV of charge-voltage compliance. 0 = Adds 0mV of charge-voltage compliance, 1024mV min. 1 = Adds 64mV of charge-voltage compliance. 0 = Adds 0mV of charge-voltage compliance, 1024mV min. 1 = Adds 128mV of charge-voltage compliance. 0 = Adds 0mV of charge-voltage compliance, 1024mV min. 1 = Adds 256mV of charge-voltage compliance. 0 = Adds 0mV of charge-voltage compliance, 1024mV min. 1 = Adds 512mV of charge-voltage compliance. 0 = Adds 0mV of charge-voltage compliance. 1 = Adds 1024mV of charge-voltage compliance. 0 = Adds 0mV of charge-voltage compliance. 1 = Adds 2048mV of charge-voltage compliance. 0 = Adds 0mV of charge-voltage compliance. 1 = Adds 4096mV of charge-voltage compliance. 0 = Adds 0mV of charge-voltage compliance. 1 = Adds 8192mV of charge-voltage compliance. 0 = Adds 0mV of charge-voltage compliance. 1 = Adds 16384mV of charge-voltage compliance, 19200mV max. Not used. Normally a 32768mV weight.
Command: 0x15
Charger Timeout
CHARGE-VOLTAGE SET POINT (mV)
19200
The MAX1535A includes a timer that terminates charging if the charger has not received a ChargeVoltage() or ChargeCurrent() command in 175s. During charging, the timer is reset each time a ChargeVoltage() or ChargeCurrent() command is received; this ensures that the charging cycle is not terminated.
16800
8400
Thermistor Comparators
Four thermistor comparators evaluate the voltage at the THM input to determine the battery temperature. This input is meant to be used with the internal thermistor connected to ground inside the battery pack. Connect the output of the battery thermistor to THM. Connect a pullup resistor from THM to VDD. The resistive voltagedivider sets the voltage at THM.
24
4200
1024 0x0400 0x1060 0x20D0 0x41A0 0x4B00 0xFFFF
CHARGEVOLTAGE() CODE
Figure 7. ChargeVoltage() Code to Charge-Voltage Set Point Mapping
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Highly Integrated Level 2 SMBus Battery Charger
Table 8. AlarmWarning()
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BIT NAME Error Code Error Code Error Code Error Code FULLY_DISCHARGED FULLY_CHARGED DISCHARGING INITIALIZING REMAINING_TIME_ALARM REMAINING_CAPACITY_ALARM Reserved TERMINATE_DISCHARGE_ALARM OVER_TEMP_ALARM OTHER_ALARM TERMINATE_CHARGE_ALARM OVER_CHARGE_ALARM Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used 0 = Charge normally. 1 = Terminate charging. 0 = Charge normally. 1 = Terminate charging. 0 = Charge normally. 1 = Terminate charging. 0 = Charge normally. 1 = Terminate charging. DESCRIPTION
MAX1535A
Command: 0x16
Thermistor Bits
Table 10 summarizes the conditions for setting the thermistor bits and how these 4 bits affect the charging status when a 10k pullup resistor is connected between VDD and THM: * THERMISTOR_OR bit is set when the thermistor value is greater than 100k. This indicates that the thermistor is open or a battery is not present. The charger is set to POR, and the BATTERY_PRESENT bit is cleared. * THERMISTOR_COLD bit is set when the thermistor value is greater than 30k. The thermistor indicates a cold battery. This bit does not affect charging. * THERMISTOR_HOT bit is set when the thermistor value is less than 3k. This is a latched bit and is cleared by removing the battery or sending a POR with the ChargerMode() command. The charger is terminated unless the HOT_STOP bit is cleared in the ChargerMode() command or the THERMISTOR_UR bit is set. See Tables 4 and 10. * THERMISTOR_UR bit is set when the thermistor value is less than 500 (i.e., THM is grounded).
11008
INPUT-CURRENT SET POINT (mA)
8192
4096
256 0x080 0x0800 0x1000 0x1580 0xFFFF
INPUTCURRENT() CODE
Figure 8. InputCurrent() Code to Input Current-Limit Mapping
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Highly Integrated Level 2 SMBus Battery Charger MAX1535A
Multiple bits may be set depending on the value of the thermistor (e.g., a thermistor that is 450 causes both the THERMISTOR_HOT and the THERMISTOR_UR bits to be set). The thermistor may be replaced with fixedvalue resistors in battery packs that do not require the thermistor as a secondary fail-safe indicator. In that case, it is the responsibility of the battery pack electronics to manipulate the resistance to obtain correct charger behavior. ous conduction mode for improved light-load efficiency. The operation of the DC-to-DC controller is determined by the following four comparators as shown in the functional diagram in Figure 9: * IMIN. Compares the control signal (LVC) against 100mV (typ). When LVC voltage is less than 100mV, the comparator output is low and a new cycle cannot start. * CCMP. Compares LVC against the charge-current feedback signal (CSI). The comparator output is high and the high-side MOSFET on-time is terminated when the CSI voltage is higher than LVC. * IMAX. Compares CSI to 2V (corresponding to 10A when R2 = 10m). The comparator output is high and the high-side MOSFET on-time is terminated when CSI voltage is higher than the threshold. A new cycle cannot start until the IMAX comparator output goes low. * ZCMP. Compares CSI to 100mV (corresponding to 500mA when R2 = 10m). The comparator output is high and both MOSFETs are turned off when CSI voltage is lower than the threshold.
AC Adapter Detection and Power Source Selection
The MAX1535A includes a hysteretic comparator that detects the presence of an AC power adapter. The MAX1535A automatically delivers power to the system load from an appropriate available power source. When the adapter is present, the open-drain ACOK output becomes high impedance and the P-channel source switch (P3 in Figure 1) is turned on by PDS, thereby powering the system. The switch threshold at ACIN is 2.048V. Use a resistive voltage-divider from the adapter's output to the ACIN pin to set the appropriate detection threshold. When charging, the battery is isolated from the system load with the P-channel load switch (P2 in Figure 1), which is switched off by PDL. When the adapter is absent, the drive to the switches changes state in a fast break-before-make sequence. PDL begins to turn on 7.5s after PDS begins to turn off. The threshold for selecting between the PDL and PDS switches is set based on the voltage difference between the DCIN and the BATT pins. If this voltage difference drops below 100mV, the PDS is switched off and PDL is switched on. Under these conditions, the MAX1535A is completely powered down. The PDL switch is kept on with a 100k pulldown resistor when the AC adapter is removed. The drivers for PDL and PDS are fully integrated. The positive bias inputs for the drivers connect to the SRC pin and the negative bias inputs connect to a negative regulator referenced to SRC. With this arrangement, the drivers can swing from SRC to approximately 10V below SRC.
CCV, CCI, CCS, and LVC Control Blocks
The MAX1535A controls input current (CCS control loop), charge current (CCI control loop), or charge voltage (CCV control loop), depending on the operating condition. The three control loops, CCV, CCI, and CCS, are brought together internally at the lowest voltage clamp (LVC) amplifier. The output of the LVC amplifier is the feedback control signal for the DC-to-DC controller. The minimum voltage at CCV, CCI, or CCS appears at the output of the LVC amplifier and clamps the other two control loops to within 0.3V above the control point. Clamping the other two control loops close to the lowest control loop ensures fast transition with minimal overshoot when switching between different control loops (see the Compensation section).
Continuous-Conduction Mode
With sufficient charge current, the MAX1535A inductor current never reaches zero, which is defined as continuous-conduction mode. The regulator switches at 400kHz (nominal) if it is not in dropout (VBATT < 0.88 x VDCIN). The controller starts a new cycle by turning on the high-side P-channel MOSFET and turning off the low-side N-channel MOSFET. When the charge-current feedback signal (CSI) is greater than the control point (LVC), the CCMP comparator output goes high and the controller initiates the off-time by turning off the highside P-channel MOSFET and turning on the low-side Nchannel MOSFET. The operating frequency is governed
DC-to-DC Converter
The MAX1535A employs a synchronous step-down DCto-DC converter with a P-channel high-side MOSFET switch and an N-channel low-side synchronous rectifier. The MAX1535A features a pseudofixed-frequency, current-mode control scheme with cycle-by-cycle current limit. The off-time is dependent upon V DCIN , VBATT, and a time constant, with a minimum tOFF of 300ns. The MAX1535A can also operate in discontinu-
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Highly Integrated Level 2 SMBus Battery Charger
Table 9. InputCurrent()
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BIT NAME -- -- -- -- -- -- -- Input Current, DACS 0 Input Current, DACS 1 Input Current, DACS 2 Input Current, DACS 3 Input Current, DACS 4 Input Current, DACS 5 -- -- -- DESCRIPTION Not used. Normally a 2mA weight. Not used. Normally a 4mA weight. Not used. Normally an 8mA weight. Not used. Normally a 16mA weight. Not used. Normally a 32mA weight. Not used. Normally a 64mA weight. Not used. Normally a 128mA weight. 0 = Adds 0mA of input-current compliance. 1 = Adds 256mA of input-current compliance. 0 = Adds 0mA of input-current compliance. 1 = Adds 512mA of input-current compliance. 0 = Adds 0mA of input-current compliance. 1 = Adds 1024mA of input-current compliance. 0 = Adds 0mA of input-current compliance. 1 = Adds 2048mA of input-current compliance. 0 = Adds 0mA of input-current compliance. 1 = Adds 4096mA of input-current compliance. 0 = Adds 0mA of input-current compliance. 1 = Adds 8192mA of input-current compliance. Not used. Normally a 16384mA weight. Not used. Normally a 32768mA weight. Not used. Normally a 65536mA weight.
MAX1535A
Command: 0x3F
Table 10. Thermistor Bit Settings
THERMISTOR STATUS BIT THERMISTOR_OR THERMISTOR_COLD (NONE) THERMISTOR_HOT THERMISTOR_UR DESCRIPTION Overrange Cold Normal Hot Underrange CONDITIONS RTHM > 100k or VTHM > 0.91 x VDD RTHM > 30k or VTHM > 0.75 x VDD 3k < RTHM < 30k or 0.23 x VDD < VTHM < 0.75 x VDD RTHM < 3k or VTHM < 0.23 x VDD RTHM < 500 or VTHM < 0.05 x VDD WAKE-UP CHARGE Not allowed Allowed for timeout period Allowed for timeout period Not allowed Allowed CONTROLLED CHARGE Not allowed Allowed Allowed Not allowed Allowed
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27
Highly Integrated Level 2 SMBus Battery Charger MAX1535A
by the off-time and is dependent upon V DCIN and VBATT. The off-time is set by the following equation: V -V t OFF = 2.5s x DCIN BATT VDCIN The on-time can be determined using the following equation: t ON = L x IRIPPLE VCSSN - VBATT Discontinuous Conduction The MAX1535A enters discontinuous-conduction mode when the output of the LVC control point falls below 100mV. For R2 = 10m, this corresponds to 0.5A: IMIN = 0.1V = 0.5 A ch arg e current for R2 = 10m 20 x 2R2
w h e r eRIPPLE = I
VBATT xt OFF . L
In discontinuous mode, a new cycle is not started until the LVC voltage rises above 100mV. Discontinuous mode operation can occur during conditioning charge of overdischarged battery packs, when the charge current has been reduced sufficiently by the CCS control loop, or when the charger is in constant-voltage mode with a nearly full battery pack.
The switching frequency can then be calculated: fSW = 1 t ON + t OFF
Compensation
The charge voltage, charge current, and input currentlimit regulation loops are compensated separately and independently at the CCV, CCI, and CCS pins. CCV Loop Compensation The simplified schematic in Figure 10 is sufficient to describe the operation of the MAX1535A when the voltage loop (CCV) is in control. The required compensation network is a pole-zero pair formed with CCV and RCV. The pole is necessary to roll off the voltage loop's response at low frequency. The zero is necessary to compensate the pole formed by the output capacitor and the load. RESR is the equivalent series resistance (ESR) of the charger output capacitor (COUT). RL is the equivalent charger output load, where RL = VBATT / ICHG. The equivalent output impedance of the GMV amplifier, ROGMV, is greater than 10M. The voltage amplifier transconductance, GMV = 0.125A/mV. The DC-to-DC converter transconductance is dependent upon the charge current-sense resistor R2: GMOUT = 1 A CSI x R2
These equations describe the controller's pseudofixedfrequency performance over the most common operating conditions. At the end of the fixed off-time, the controller initiates a new cycle if the control point (LVC) is greater than 100mV (IMIN comparator output is high), and the peak charge current is less than the cycle-by-cycle limit (IMAX comparator output is low). If the peak charge current exceeds the IMAX comparator threshold, the on-time is terminated. The IMAX comparator governs the maximum cycle-by-cycle current limit and is internally set to 10A (when R2 = 10m). The cycle-by-cycle current limit effectively protects against sudden overcurrent faults. If during the off-time the inductor current goes to zero, the ZCMP comparator output pulls high, turning off the low-side MOSFET. Both the high- and low-side MOSFETs are turned off until another cycle is ready to begin. The MAX1535A enters into the discontinuous conduction mode (see the Discontinuous Conduction section). There is a 0.3s minimum off-time when the (VDCIN VBATT) differential becomes too small. If VBATT 0.88 x V DCIN , then the threshold for minimum off-time is reached and the off-time is fixed at 0.27s. The switching frequency in this mode varies according to the equation: f= 1 L x IRIPPLE + 0.27s (VCSSN - VBATT )
where ACSI = 20, and R2 = 0.01 in the typical application circuits, so GMOUT = 5A/V. The loop transfer function (LTF) is given by:
LTF = GMOUT x RL x GMV x ROGMV x (1 + SCOUT x RESR )(1 + SCCV x RCV ) (1 + SCCV x ROGMV )(1 + SCOUT x RL )
The poles and zeros of the voltage-loop transfer function are listed from lowest to highest frequency in Table 11. Near crossover CCV is much lower impedance than ROGMV. Since CCV is in parallel with ROGMV, CCV dominates the parallel impedance near crossover.
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Highly Integrated Level 2 SMBus Battery Charger
Additionally, RCV is much higher impedance than CCV and dominates the series combination of RCV and CCV, so: ROGMV x (1 + SCCV x RCV ) RCV (1 + SCCV x ROGMV ) C OUT is also much lower impedance than RL near crossover so the parallel impedance is mostly capacitive and: RL (1 + SCOUT x RL ) 1 SCOUT
ZCMP 50mV DCIN BATT OFF-TIME COMPUTE OFF-TIME ONE-SHOT LVC
MAX1535A
CSI IMAX 2V R Q TO DH DRIVER
CCMP
IMIN 100mV
R
Q
TO DL DRIVER
If RESR is small enough, its associated output zero has a negligible effect near crossover and the loop-transfer function can be simplified as follows: LTF = GMOUT x RCV GMV SCOUT
Figure 9. DC-to-DC Converter Block Diagram
Setting the LTF = 1 to solve for the unity-gain frequency yields: fCO _ CV = GMOUT x GMV x RCV 2 x COUT
BATT GMOUT RESR COUT GMV RCV ROGMV REF RL
For stability, choose a crossover frequency lower than 1/10th of the switching frequency. For example, choose a crossover frequency of 30kHz and solving for RCV using the component values listed in Figure 1 yields RCV = 20k: RCV = 2 x COUT x fCO _ CV GMV x GMOUT = 10k
CCV
CCV
VBATT = 16.8V GMV = 0.125A/mV ICHG = 4A GMOUT = 5A/V COUT = 2 x 22F fOSC = 400kHz RL = 0.2 fCO_CV = 30kHz
Figure 10. CCV Loop Diagram
To ensure that the compensation zero adequately cancels the output pole, select fZ_CV fP_OUT: CCV (RL/RCV) COUT CCV 4nF (assuming 4 cells and 4A maximum charge current) Figure 11 shows the Bode plot of the voltage-loop frequency response using the values calculated above.
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Highly Integrated Level 2 SMBus Battery Charger MAX1535A
Table 11. CCV Loop Poles and Zeros
NAME CCV pole EQUATION DESCRIPTION Lowest frequency pole created by CCV and GMV's finite output resistance. Since ROGMV is very large and not well controlled, the exact value for the pole frequency is also not well controlled (ROGMV > 10M). Voltage-loop compensation zero. If this zero is at the same frequency or lower than the output pole fP_OUT, then the loop-transfer function approximates a single-pole response near the crossover frequency. Choose CCV to place this zero at least one decade below crossover to ensure adequate phase margin. Output pole formed with the effective load resistance RL and the output capacitance COUT. RL influences the DC gain but does not affect the stability of the system or the crossover frequency. Output ESR Zero. This zero can keep the loop from crossing unity gain if fZ_OUT is less than the desired crossover frequency; therefore, choose a capacitor with an ESR zero greater than the crossover frequency.
fP _ CV =
1 2ROGMV x CCV
CCV zero
1 fZ _ CV = 2RCV x CCV
Output pole
fP _ OUT =
1 2RL x COUT 1 2RESR x COUT
Output zero
fZ _ OUT =
80 60 40 20 0 -20 -40 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) MAG PHASE
0
CSIP GMOUT CSIN RS2
-45
PHASE (DEGREES)
MAGNITUDE (dB)
CSI
-90
CCI GMI
-135 1M
CCI
ROGMI ICTL
Figure 11. CCV Loop Response
Figure 12. CCI Loop Diagram
CCI Loop Compensation The simplified schematic in Figure 12 is sufficient to describe the operation of the MAX1535A when the battery current loop (CCI) is in control. Since the output capacitor's impedance has little effect on the response of the current loop, only a simple single pole is required to compensate this loop. ACSI is the internal gain of the current-sense amplifier. R2 is the charge current-sense resistor, R2 = 10m. ROGMI is the equivalent output
impedance of the GMI amplifier, which is greater than 10M. GMI is the charge-current amplifier transconductance = 1A/mV. GMOUT is the DC-to-DC converter transconductance = 5A/V. The loop-transfer function is given by: LTF = GMOUT x ACSI x RS2 x GMI ROGMI 1 + SROGMI x CCI
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Highly Integrated Level 2 SMBus Battery Charger
This describes a single-pole system. Since: GMOUT = 1 ACSI x RS2 The crossover frequency is given by: fCO _ CS = GMS 2CCS
MAX1535A
the loop-transfer function simplifies to: LTF = GMI ROGMI 1 + SROGMI x CCI
The crossover frequency is given by: fCO _ CI = GMI 2CCI
For stability, choose a crossover frequency lower than 1/10th of the switching frequency: CCS = 5xGMS / (2 fOSC) Choosing a crossover frequency of 30kHz and using the component values listed in Figure 1 yields CCS > 5.4nF. Values for CCS greater than 10 times the minimum value may slow down the current-loop response excessively. Figure 15 shows the Bode plot of the input current-limit-loop frequency response using the values calculated above.
For stability, choose a crossover frequency lower than 1/10th of the switching frequency: CCI = GMI / (2 fCO-CI) Choosing a crossover frequency of 30kHz and using the component values listed in Figure 1 yields CCI > 5.4nF. Values for CCI greater than 10 times the minimum value may slow down the current-loop response excessively. Figure 13 shows the Bode plot of the current-loop frequency response using the values calculated above. CCS Loop Compensation The simplified schematic in Figure 14 is sufficient to describe the operation of the MAX1535A when the input current-limit loop (CCS) is in control. Since the output capacitor's impedance has little effect on the response of the input current-limit loop, only a single pole is required to compensate this loop. ACSS is the internal gain of the current-sense amplifier. R1 is the input current-sense resistor, R1 = 10m in the typical application circuits. ROGMS is the equivalent output impedance of the GMS amplifier, which is greater than 10M. GMS is the charge-current amplifier transconductance = 1A/mV. GMIN is the DC-to-DC converter's input-referred transconductance = (1/D) x GMOUT = (1/D) x 5A/V. The loop-transfer function is given by: LTF = GMIN x A CSS x RSI x GMS Since GMIN = simplifies to : LTF = GMS ROGMS 1 + SROGMS x CCS ROGMS 1+ SROGMS x CCS
MOSFET Drivers
The DHI and DLO outputs are optimized for driving moderate-sized power MOSFETs. The MOSFET drive capability is the same for both the low-side and highside switches. This is consistent with the variable duty factor that occurs in the notebook computer environment where the battery voltage changes over a wide range. An adaptive dead-time circuit monitors the DLO output and prevents the high-side FET from turning on until DLO is fully off. There must be a low-resistance, low-inductance path from the DLO driver to the MOSFET gate for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry in the MAX1535A interprets the MOSFET gate as "off" while there is still charge left on the gate. Use very short, wide traces measuring 10 squares to 20 squares or less (1.25mm to 2.5mm wide if the MOSFET is 25mm from the device). Unlike the DLO output, the DHI output uses a 50ns (typ) delay time to prevent the low-side MOSFET from turning on until DHI is fully off. The same layout considerations should be used for routing the DHI signal to the highside MOSFET. Since the transition time for a P-channel switch can be much longer than an N-channel switch, the dead time prior to the high-side P-channel MOSFET turning on is more pronounced than in other synchronous step-down regulators, which use high-side N-channel switches. On the high-to-low transition, the voltage on the inductor's "switched" terminal flies below ground until the low-side switch turns on. A similar dead-time spike occurs on the opposite low-to-high transition. Depending upon the magnitude of the load current, these spikes usually have a minor impact on efficiency. The high-side driver (DHI) swings from SRC to 5V below SRC and has a typical impedance of 1 sourcing and 4 sinking. The low-side driver (DLO) swings
31
1 , the loop - transfer function A CSS x RS1
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Highly Integrated Level 2 SMBus Battery Charger MAX1535A
100 80 MAGNITUDE (dB) 60 40 -45 20 0 -20 -40 0.1 10 1k FREQUENCY (Hz) 100k -90 10M CCS CCS ROGMS GMIN SYSTEM LOAD MAG PHASE PHASE (DEGREES) CLS 0 ADAPTER INPUT CSSP CSS RS1 CSSN GMS
Figure 13. CCI Loop Response
Figure 14. CCS Loop Diagram
40 -45 20 0 -20 -40 0.1 10 1k FREQUENCY (Hz) 100k -90 10M
Design Procedure
Table 12 lists the recommended components and refers to the circuit of Figure 1. The following sections describe how to select these components.
MOSFET Selection
MOSFETs P2 and P3 (Figure 1) provide power to the system load when the AC adapter is inserted. These devices may have modest switching speeds, but must be able to deliver the maximum input current as set by R1. As always, care should be taken not to exceed the device's maximum voltage ratings at the maximum operating temperature. The P-channel/N-channel MOSFETs (P1, N1) are the switching devices for the step-down regulator. The guidelines for these devices focus on the challenge of obtaining high load-current capability when using highvoltage (>20V) AC adapters. Low-current applications usually require less attention. The high-side MOSFET (P1) must be able to dissipate the resistive losses plus the switching losses at both V DCIN(MIN) and VDCIN(MAX). Calculate both these sums.
Figure 15. CCS Loop Response
Ideally, the losses at V DCIN(MIN) should be roughly equal to losses at V DCIN(MAX) , with lower losses in between. If the losses at VDCIN(MIN) are significantly higher than the losses at VDCIN(MAX), consider increasing the size of P1. Conversely, if the losses at VDCIN(MAX) are significantly higher than the losses at V IN(MIN) , consider reducing the size of P1. If DCIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET that has
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PHASE (DEGREES)
MAGNITUDE (dB)
from DLOV to ground and has a typical impedance of 1 sinking and 4 sourcing. This helps prevent DLO from being pulled up when the high-side switch turns on due to capacitive coupling from the drain to the gate of the low-side MOSFET. This places some restrictions on the MOSFETs that can be used. Using a low-side MOSFET with smaller gate-to-drain capacitance can prevent these problems.
100 80 60 MAG PHASE
0
Highly Integrated Level 2 SMBus Battery Charger
the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., one or two 8-pin SO, DPAK, or D2PAK), and is reasonably priced. Make sure that the DLO gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems can occur. Since the MAX1535A utilizes P-channel high-side and N-channel low-side MOSFETs, the switching characteristics can be quite different. Select devices that have short turn-off times, and make sure that P1(tDOFF(MAX)) - N1(tDON(MIN)) < 40ns. Failure to do so may result in efficiency-killing shoot-through currents. If delay mismatch causes shoot-through currents, consider adding capacitance from gate to source on N1 to slow down its turn-on time. Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied due to the squared term in the C x VDCIN2 x fSW switching-loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low-battery voltages becomes extraordinarily hot when biased from V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (N1), the worst-case power dissipation always occurs at maximum input voltage: V I 2 PD(LOW - SIDE) = 1- BATT LOAD x RDS(ON) VDCIN 2 Choose a Schottky diode (D1, Figure 1) having a forward voltage low enough to prevent the N1 MOSFET body diode from turning on during the dead time. As a general rule, a diode having a DC current rating equal to 1/3 of the load current is sufficient. This diode is optional and can be removed if efficiency is not critical.
MAX1535A
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET, the worst-case power dissipation (PD) due to resistance occurs at the minimum supply voltage: V I 2 PD(HIGH - SIDE) = BATT LOAD x RDS(ON) VDCIN 2 Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. The optimum occurs when the switching (AC) losses equal the conduction (R DS(ON)) losses. High-side switching losses do not usually become an issue until the input is greater than approximately 15V. Calculating the power dissipation in P1 due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turnoff times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including a verification using a thermocouple mounted on P1:
PD(HS _ SWITCHING) = VDCIN(MAX)2 x CRSS x fSW x ILOAD 2 x IGATE
Inductor Selection
The charge current, ripple, and operating frequency (off-time) determine the inductor characteristics. Inductor L1 must have a saturation current rating of at least the maximum charge current plus 1/2 of the ripple current (IL): ISAT = ICHG + (1/2) IL The ripple current is determined by: IL = VBATT x tOFF / L If VBATT < 0.88VDCIN, then: tOFF = 2.5s (VDCIN - VBATT) / VDCIN or: tOFF = 0.27s (typ) for VBATT > 0.88 VDCIN Figure 16 illustrates the variation of the ripple current vs. battery voltage when the circuit is charging at 3A with a fixed input voltage of 19V. Higher inductor values decrease the ripple current. Smaller inductor values require high-saturation current capabilities and degrade efficiency. Designs that set LIR = IL / ICHG = 0.3 usually result in a good balance between inductor size and efficiency: V x t OFF L = BATT LIR x ICHG
where CRSS is the reverse transfer capacitance of P1, and IGATE is the peak gate-drive source/sink current (4.5A sourcing and 1.1A sinking).
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33
Highly Integrated Level 2 SMBus Battery Charger MAX1535A
Table 12. Recommended Components
DESIGNATION C1-C4 QTY 4 DESCRIPTION 22F 20%, 25V X5R ceramic capacitors (2220) TDK C5750X5R1E226M 1F 10%, 25V X7R ceramic capacitors (1206) Murata GRM31MR71E105K Taiyo Yuden TMK316BJ105KL TDK C3216X7R1E105K 1F 10%, 16V X7R ceramic capacitors (0805) Murata GRM21BR71C105K Taiyo Yuden EMK212BJ105KG TDK C2012X7R1E105K 0.1F 10%, 25V X7R ceramic capacitors (0603) Murata GRM188R71E104K TDK C1608X7R1E104K 0.01F 10%, 16V X7R ceramic capacitors (0402) Murata GRP155R71E103K Taiyo Yuden EMK105BJ103KV TDK C1005X7R1E103K Schottky diode, 0.5A, 30V, SOD-123 Diodes Inc. B0530W General Semiconductor MBR0530 ON Semiconductor MBR0530 4.3H, 11A, 11.4m inductor Sumida CEP125-4R3MC-U MOSFET, N-channel, 13.5A, +30V, 8-pin SO Fairchild FDS6670S MOSFET, P-channel, 13A, -30V, 8-pin SO Fairchild FDS6679Z 10m 1%, 1W sense resistor (2512) IRC LRC-LRF2512-01-R010-F 365k 1% resistor (0805) 49.9k 1% resistor (0805) 1M 5% resistor (0805) 20k 5% resistor (0603) 10k 5% resistors (0805) 33 5% resistor (0805) 1M potentiometers (multiturn) Bourns 3266W-1-105 or equivalent
C5, C6
2
C7, C8, C9
3
C10, C11
2
C12, C13, C14
3
D1
1
L1 N1 P1-P4 R1, R2 R3 R4 R5 R6 R7-R10 R11 R12, R13
1 1 4 2 1 1 1 1 4 1 2
34
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Highly Integrated Level 2 SMBus Battery Charger
Applications Information
1.5 3 CELLS (12.6V) 4 CELLS (16.8V) RIPPLE CURRENT (A) 1.0
MAX1535A
Smart-Battery System Background Information
Smart-battery systems have evolved since the conception of the smart-battery system (SBS) specifications. Originally, such systems consisted of a smart battery and smart-battery charger that were compatible with the SBS specifications and communicated directly with each other using SMBus protocols. Modern systems still employ the original commands and protocols, but often use a keyboard controller or similar digital intelligence to mediate the communication between the battery and the charger (Figure 17). This arrangement permits considerable freedom in the implementation of charging algorithms at the expense of standardization. Algorithms can vary from the simple detection of the battery with a fixed set of instructions for charging the battery to highly complex programs that can accommodate multiple battery configurations and chemistries. Microcontroller programs can perform frequent tests on the battery's state of charge and dynamically change the voltage and current applied to enhance safety. Multiple batteries can also be utilized with a selector that is programmable over the SMBus. Batteries that use SMBus fuel gauges must sometimes perform a conditioning cycle to calibrate the fuel gauge's reference data for empty and full capacity. This cycle consists of isolating the battery from the charger and discharging it through the system load. When the battery reaches 100% depth of discharge, it is then recharged. The circuit in Figure 1 is capable of implementing this feature under software control. To utilize the conditioning function, the configuration of the PDS switch must be changed to source-connected FETs to prevent the AC adapter from supplying current to the system through the MOSFET's body diode. The SRC pin must be connected to the common source node of the back-to-back FETs to properly drive the MOSFETs. It is essential to alert the user that the system is performing a conditioning cycle. If the user terminates the cycle prematurely, the battery may be discharged even though the system was running off an AC adapter for a substantial period of time. If the AC adapter is in fact removed during conditioning, the MAX1535A keeps the PDL switch on and the charger remains off as it would in normal operation. If the battery is removed during conditioning mode, the PDS switch is turned back on and the system is powered from the AC adapter.
0.5 L = 10H VDCIN = 19V CHARGE CURRENT = 3A 0 8 9 10 11 12 13 14 15 16 17 18 VBATT (V)
Figure 16. Ripple Current vs. Battery Voltage
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. Nontantalum chemistries (ceramic, aluminum, or OSCON) are preferred due to their resilience to power-up surge currents: V BATT (VDCIN - VBATT ) IRMS = ICHG VDCIN The input capacitors should be sized so that the temperature rise due to ripple current in continuous conduction does not exceed approximately 10C. The maximum ripple current occurs at 50% duty factor or VDCIN = 2 x VBATT, which equates to 0.5 x ICHG. If the application of interest does not achieve the maximum value, size the input capacitors according to the worstcase conditions.
Output Capacitor Selection
The output capacitor absorbs the inductor ripple current and must tolerate the surge current delivered from the battery when it is initially plugged into the charger. As such, both capacitance and ESR are important parameters in specifying the output capacitor as a filter and to ensure the stability of the DC-to-DC converter (see the Compensation section.) Beyond the stability requirements, it is often sufficient to make sure that the output capacitor's ESR is much lower than the battery's ESR. Either tantalum or ceramic capacitors can be used on the output. Ceramic devices are preferable because of their good voltage ratings and resilience to surge currents.
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35
Highly Integrated Level 2 SMBus Battery Charger MAX1535A
Setting Input Current Limit
The input current limit should be set based on the current capability of the AC adapter and the tolerance of the input current limit. The upper limit of the input current threshold should never exceed the adapter's minimum available output current. For example, if the adapter's output current rating is 5A 10%, the input current limit should be selected so that its upper limit is less than 5A x 0.9 = 4.5A. Since the input current-limit accuracy of the MAX1535A is 5%, the typical value of the input current limit should be set at 4.5A / 1.05 4.28A. The lower limit for input current must also be considered. For chargers at the low end of the specification, the input current limit for this example could be 4.28A x 0.95, or approximately 4.07A.
AC LINE AC-TO-DC CONVERTER (ADAPTER) SYSTEM POWER SUPPLIES
MAX1535 SMART-BATTERY CHARGER/ POWER-SOURCE SELECTOR SMBus CONTROL SIGNALS FOR BATTERY
BATT+ SMART BATTERY
BATT-
Setting VMAX and IMAX Limits
The VMAX and IMAX limits should be determined based on the design values of the maximum current and voltage in the battery and the accuracy of VMAX and IMAX limits. The VMAX function is intended to be a secondary protection mechanism. So it is not relevant whether SMBus or VMAX controls the charger, so long as the charge voltage is below the battery manufacturer's maximum ratings. The SMBus and VMAX thresholds can therefore overlap slightly because chargevoltage accuracy is critical for safely and efficiently charging the battery. The lower limit of the VMAX threshold should be equal to the normal charge voltage of 4.20V per cell. Assuming the accuracy of the VMAX threshold is 5%, the typical value of the VMAX limit should be set at 4.20 / 0.95 = 4.42V per cell. For a 4cell battery pack, the nominal VMAX limit is 4 x 4.42V = 17.68V. The accuracy of the charge current is not as critical as the charge voltage. Small variations (such as 5%) in the absolute value of the charge current do not have a significant effect on the total charge time. It is acceptable to have the maximum charge current set by SMBus and the IMAX limit overlap slightly. Assuming the maximum charge current is 5A 5% and the accuracy of the IMAX threshold is 5%, the lower limit of the IMAX threshold can be set equal to the upper limit of the maximum charge current (5.25A), or slightly lower. Therefore, the typical value of the IMAX limit should be 5.25A / 0.95 = 5.53A, or slightly lower.
SMBus CONTROL SIGNALS FOR BATTERY
SYSTEM HOST (KEYBOARD CONTROLLER)
Figure 17. Typical Smart-Battery System
Layout and Bypassing
Bypass DCIN with a 1F ceramic capacitor to ground (Figure 1). D4 protects the MAX1535A when the DC power source input is reversed. A signal diode for D1 is adequate because DCIN only powers the LDO and the internal reference. Bypass V DD , DCIN, LDO, DHIV, DLOV, SRC, DAC, and REF as shown in Figure 1. Good PC board layout is required to achieve specified noise immunity, efficiency, and stable performance. The PC board layout artist must be given explicit instructions--preferably a sketch showing the placement of the power-switching components and high-current routing. Refer to the PC board layout in the MAX1535A evaluation kit for examples. A ground plane is essential for optimum performance. In most applications, the circuit is located on a multilayer board, and full use of the four or more copper layers is recommended. Use the top layer for high-current connections, the bottom layer for quiet connections, and the inner layers for uninterrupted ground planes.
36
______________________________________________________________________________________
Highly Integrated Level 2 SMBus Battery Charger
Use the following step-by-step guide: 1) Place the high-power connections first, with their grounds adjacent: * Minimize the current-sense resistor trace lengths, and ensure accurate current sensing with Kelvin connections. * Minimize ground trace lengths in the high-current paths. * Minimize other trace lengths in the high-current paths. * Use >5mm wide traces in the high-current paths. * Connect C1 and C2 to the high-side MOSFET (10mm, max length). * Minimize the LX node (MOSFETs, rectifier cathode, inductor (15mm, max length)). Ideally, surface-mount power components are flush against each other with their ground terminals almost touching. These high-current grounds are then connected to each other with a wide, filled zone of top-layer copper, so they do not go through vias. The resulting top-layer subground plane is connected to the normal inner-layer ground plane at the output ground terminals, which ensures that the IC's analog ground is sensing at the supply's output terminals without interference from IR drops and ground noise. Other high-current paths should also be minimized, but focusing primarily on short ground and current-sense connections eliminates about 90% of all PC board layout problems. 2) Place the IC and signal components. Keep the main switching node (LX node) away from sensitive analog components (current-sense traces and the REF capacitor). Important: The IC must be no further than 10mm from the current-sense resistors. Quiet connections to REF, VMAX, IMAX, CCV, CCI, CCS, ACIN, and DCIN should be returned to a separate ground (GND) island. The appropriate traces are marked on the schematic with the ground symbol. There is very little current flowing in these traces, so the ground island need not be very large. When placed on an inner layer, a sizable ground island can help simplify the layout because the low-current connections can be made through vias. The ground pad on the backside of the package should also be connected to this quiet ground island. 3) Keep the gate drive traces (DHI and DLO) as short as possible (L < 20mm), and route them away from the current-sense lines and REF. These traces should also be relatively wide (W > 1.25mm). 4) Place ceramic bypass capacitors close to the IC. The bulk capacitors can be placed further away. Place the current-sense input filter capacitors under the part, connected directly to the GND pin. 5) Use a single-point star ground placed directly below the part at the PGND pin. Connect the power ground (ground plane) and the quiet ground island at this location. See Figure 18 for a layout example.
MAX1535A
Chip Information
TRANSISTOR COUNT: 11,900 PROCESS: BiCMOS
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37
Highly Integrated Level 2 SMBus Battery Charger MAX1535A
VIA CONNECTING POWER GROUND TO QUIET ANALOG GROUND
HIGH-CURRENT PGND PLANE
QUIET GND ISLAND
KELVIN-SENSE VIAS UNDER THE SENSE RESISTOR (REFER TO EVALUATION KIT) INDUCTOR
COUT
COUT CIN
OUTPUT
INPUT GND
Figure 18. MAX1535A PC Board Layout Example
38
______________________________________________________________________________________
Highly Integrated Level 2 SMBus Battery Charger
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX1535A
0.15 C A
D2
C L
D
b D2/2
0.10 M C A B
PIN # 1 I.D.
D/2
0.15 C B
k
PIN # 1 I.D. 0.35x45
E/2 E2/2 E (NE-1) X e
C L
E2
k L
DETAIL A
e (ND-1) X e
DETAIL B
e
L1
L
C L
C L
L
L
e 0.10 C A 0.08 C
e
C
A1
A3
PACKAGE OUTLINE 16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm
21-0140
E
1
2
COMMON DIMENSIONS PKG. 20L 5x5 28L 5x5 32L 5x5 40L 5x5 16L 5x5 SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A3 b D E e k L L1 N ND NE JEDEC 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.02 0.05 0.20 REF. 0 0.05 0.20 REF. PKG. CODES T1655-1 T1655-2 T2055-2 T2055-3 T2055-4 T2855-1 T2855-2 T2855-3 T2855-4 T2855-5 T2855-6 T2855-7 T3255-2 T3255-3 T3255-4 T4055-1
EXPOSED PAD VARIATIONS
D2
MIN. NOM. MAX. MIN.
E2 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.20 3.10 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.10 3.10 3.10 3.20 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.20 3.20 3.20
NOM. MAX. ALLOWED
DOWN BONDS
3.00 3.00 3.00 3.00 3.00 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.00 3.00 3.00 3.20
3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.20 3.00 3.10 3.25 2.70 3.25 2.70 2.70 3.25 2.70 3.10 3.10 3.10 3.20 3.35 2.80 3.35 2.80 2.80 3.35 2.80 3.20 3.20 3.20 3.00 3.15 2.60 3.15 2.60 2.60 3.15 2.60 3.00 3.00 3.00
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 0.80 BSC. 0.65 BSC. 0.50 BSC. 0.50 BSC. 0.40 BSC. 0.25 - 0.25 - 0.25 - 0.25 - 0.25 0.35 0.45 0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60 16 4 4 WHHB 20 5 5 WHHC 28 7 7 WHHD-1 32 8 8 WHHD-2 0.30 0.40 0.50 40 10 10 -
NO YES NO YES NO NO NO YES YES NO NO YES NO YES NO YES
3.30 3.40 3.20
3.30 3.40
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6. 10. WARPAGE SHALL NOT EXCEED 0.10 mm. PACKAGE OUTLINE 16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm
21-0140
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 39 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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